Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) Including Recessed Channel Regions

ABSTRACT

Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided.

REFERENCE TO PRIORITY APPLICATIONS

This application is a divisional of U.S. application Ser. No.12/106,683, filed Apr. 21, 2008, which is a divisional application ofU.S. application Ser. No. 10/795,653, filed Mar. 8, 2004, which claimspriority from Korean Patent Application No. 2003-25824 filed on Apr. 23,2003, the disclosures of which are hereby incorporated herein byreference.

FIELD OF THE INVENTION

The present invention relates to integrated circuit devices and methodsof fabricating the same and, more particularly, to integrated circuittransistors and methods of fabricating the same.

BACKGROUND OF THE INVENTION

As the size of conventional transistors is decreased, thecharacteristics of the device may be adversely affected. For example,transistors may experience a short channel effect. Referring now to FIG.1, a cross-section illustrating conventional transistors will bediscussed. As illustrated, conventional transistors may include a gateinsulation layer 14 on an integrated circuit substrate 10. A gateelectrode 16 may be provided on the gate insulation layer 14. Source anddrain regions 12 may be formed in the integrated circuit substrate 10 byimplanting impurities in the integrated circuit substrate 10 adjacentboth sides of the gate electrode 16. Regions between the source anddrain regions 12 define channel regions of the transistor.

In conventional transistors illustrated in FIG. 1, when a length of thechannel is decreased, the influence of the source and drain regions onthe channel region may increase. Accordingly, a short channel effect,for example, a change of a threshold voltage, an increase in a leakagecurrent and/or a punch-through between the source and drain regions mayoccur. The reduction in size of conventional transistors may be limitedby the occurrence of the short channel effect. Therefore, highlyintegrated devices may be difficult to fabricate.

Conventional silicon-on-insulator (SOI) transistors may reduce thelikelihood of the occurrence of the short channel effect. Referring nowto FIG. 2 a cross section of conventional SOI transistors will bediscussed. As illustrated, a gate insulation layer 26 is provided on aSOI layer 25. The SOI layer is provided on a buried insulation layer 22and the buried insulation layer 22 is provided on the integrated circuitsubstrate 10. A gate electrode 28 is formed on the gate insulation layer26. Source and drain regions 24 are provided in the SOI layer byimplanting impurities in the SOI layer 25 adjacent both sides of thegate electrode 28. Regions between the source and drain regions 24define channel regions of the transistor.

As illustrated in FIG. 2, a source and/or drain junction of the SOItransistor contacts the buried insulation layer 22. Accordingly, adepletion layer of the source and/or drain junction may be suppressed sothat a short channel effect and/or a leakage current may possibly bereduced. However, a floating body effect may occur in SOI transistorsbecause the SOI layer 25 is isolated by the buried insulation layer 22and an isolation layer. Thus, dispersion of heat generated fromoperating integrated circuit devices may be difficult and manufacturingcosts may be increased. Accordingly, improved integrated circuit devicesmay be desired.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide metal oxide semiconductor(MOS) transistors and methods of fabricating the same. A unit cell of aMOS transistor is provided having an integrated circuit substrate and aMOS transistor on the integrated circuit substrate. The MOS transistorincludes a source region, a drain region and a gate. The gate is betweenthe source region and the drain region. A channel region is providedbetween the source and drain regions. The channel region has a recessedregion that is lower than bottom surfaces of the source and drainregions.

In some embodiments of the present invention, first and secondinsulation patterns may be provided on the integrated circuit substrate.The first and second insulation patterns may be provided between thesource region and drain region, respectively, and the integrated circuitsubstrate. The first and second insulation patterns may further contactat least a portion of the bottom surface of the source region and thebottom surface of the drain region, respectively.

In further embodiments of the present invention, the gate may furtherinclude a gate insulation layer on the channel region and a gate patternon the gate insulation layer. The gate pattern may have sidewallsadjacent to the source and drain regions. The first and secondinsulation patterns may have sidewalls that are self-aligned to thesidewalls of the gate pattern. In certain embodiments of the presentinvention, the gate pattern may be provided in a gate opening on theintegrated circuit substrate. The gate pattern may include first andsecond inner spacers on sidewalls of the gate opening and a conductivepattern on the first and second inner spacers and the gate insulationlayer.

In still further embodiments of the present invention, an isolationlayer may be provided on the integrated circuit substrate. The isolationlayer may define an active region of the integrated circuit substrate.The insulation pattern may be electrically coupled to the isolationlayer. In certain embodiments of the present invention, a bottom surfaceof the isolation layer may be lower than a bottom surface of theinsulation pattern.

While the present invention is described above primarily with referenceintegrated circuit devices, methods of forming integrated circuitdevices are also provided herein.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross section illustrating conventional metal oxidesemiconductor field effect transistors (MOSFETs).

FIG. 2 is a cross section illustrating conventional silicon-on-insulator(SOI) MOSFETs.

FIG. 3 is a perspective view illustrating MOSFETs according to someembodiments of the present invention.

FIGS. 4A through 10A are plan views illustrating processing steps in thefabrication of MOSFETs according to further embodiments of the presentinvention.

FIGS. 4B through 10B are cross sections taken along the line A-A′ ofFIGS. 4A through 9A illustrating processing steps in the fabrication ofMOSFETs according to further embodiments of the present invention.

FIGS. 11A through 12A are plan views illustrating processing steps inthe fabrication of MOSFETs according to still further embodiments of thepresent invention taken along the line B-B′ of FIGS. 11A through 12A.

FIGS. 13A through 16A are plan views illustrating processing steps inthe fabrication of MOSFETs according to some embodiments of the presentinvention.

FIGS. 13B through 16B are cross sections taken along the line C-C′ ofFIGS. 12A through 15A illustrating processing steps in the fabricationof MOSFETs according to some embodiments of the present invention.

FIGS. 17A through 21A are plan views illustrating processing steps inthe fabrication of MOSFETs according to further embodiments of thepresent invention.

FIGS. 17B through 21B are cross sections taken along the lines D-D′ inFIGS. 17A through 21B illustrating processing steps in the fabricationof MOSFETs according to further embodiments of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as limited to theembodiments set forth herein; rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the thickness of layers and regions are exaggerated forclarity. It will be understood that when an element such as a layer,region or substrate is referred to as being “on ” another element, itcan be directly on the other element or intervening elements may also bepresent. It will be understood that when an element such as a layer,region or substrate is referred to as “under” or “beneath” anotherelement, it can be directly under the other element or interveningelements may also be present. It will be understood that when part of anelement is referred to as “outer,” it is closer to the outside of theintegrated circuit than other parts of the element. Like numbers referto like elements throughout.

Furthermore, relative terms, such as beneath, may be used herein todescribe an element's relationship to another as illustrated in theFigures. It will be understood that these terms are intended toencompass different orientations of the elements in addition to theorientation depicted in the Figures. For example, if a Figure isinverted, the elements described as “beneath” other elements would beoriented “above” these other elements. The relative terms are,therefore, intended to encompass all possible arrangements of theelements and not just the ones shown in the Figures.

It will be understood that although the terms first and second are usedherein to describe various regions, layers and/or sections, theseregions, layers and/or sections should not be limited by these terms.These terms are only used to distinguish one region, layer or sectionfrom another region, layer or section. Thus, a first region, layer orsection discussed below could be termed a second region, layer orsection, and similarly, a second region, layer or section may be termeda first region, layer or section without departing from the teachings ofthe present invention.

Embodiments of the present invention will be described below withrespect to FIG. 3 through 21B. Embodiments of the present inventionprovide transistors having a low recessed channel region relative tobottom surfaces of the source and drain regions. Thus, a channel lengthof transistors according to embodiments of the present invention may belonger relative to a gate line width, while still having a relativelyshort gate line width. Thus, the likelihood that transistors accordingto embodiments of the present invention may experience a short channeleffect and/or punch-through between the source and drain regions may bereduced. Furthermore, transistors according to embodiments of thepresent invention may provide source and drain regions having bottomsurfaces that contact at least a portion of an insulation pattern and achannel region between the source and drain regions may be connected tothe integrated circuit substrate. Accordingly, transistors according toembodiments of the present invention may provide a reduced likelihood ofthe occurrence of the short channel effect and a floating body effectand may disperse heat throughout the device during operation of thetransistor. In still further embodiments of the present invention,transistors according to embodiments of the present invention may have agate pattern having sidewalls aligned with parallel fins that includethe source and drain regions, thus, the possibility of misalignment ofthe gate pattern may be reduced. Accordingly, transistors according toembodiments of the present invention may provide improved devicecharacteristics as discussed further below.

Referring now to FIG. 3, a perspective view of transistors, according tosome embodiments of the present invention, will be discussed. Asillustrated in FIG. 3, the transistor comprises a vertical portion 33and parallel fins 35. The vertical portion 33 is provided on anintegrated circuit substrate 10. The parallel fins 35 extend from abottom portion of the vertical portion 33 as illustrated in FIG. 3.Source and drain regions are provided in each of the parallel fins 35.Regions between the source and drain regions define channel regions ofthe transistor. As further illustrated in FIG. 3, the channel region ofthe transistor is formed on a recess region and a bottom of the recessregion is lower than bottoms of the source and drain regions. Gateinsulation layers 66, 106 and 132 are provided on the channel region.Gate patterns 68, 108 and 134 a are provided on the gate insulationlayers 66, 106 and 132. The Parallel fins 35 are separated from theintegrated circuit substrate in a predetermined space. Insulationpatterns 70 and 112 are provided between the source and drain regions,i.e., between the parallel fins 35 and the integrated circuit substrate10. Sidewalls of the gate patterns 68, 108 and 134 a are verticallyaligned to sidewalls of vertical portion 33. The source and drainregions 74, 110 and 148 and insulation patterns 70 and 112 aresymmetrically arranged around the gate electrode.

As illustrated in FIG. 3, the bottom surfaces of the source and drainregions 74, 110 and 148 are higher than a bottom surface of the channelregion. Thus, although the gate pattern has minimum line width, thechannel length of the transistor may be relatively longer than a linewidth of a gate. The likelihood of the occurrence of the short channeleffect may be reduced because the bottom surfaces of the source anddrain regions 74, 110 and 148 contact the insulation patterns 70 and112, for example, oxide patterns. In addition, a floating body effectmay be controlled and heat may be adequately dispersed.

In certain embodiments of the present invention, a silicide layer may beformed on a surface of the source and drain regions 74, 110 and 148 anda surface of the gate pattern 68, 108 and 134 a. In this embodiment,contact of the silicide layer and the source and drain regions 74, 110and 148 and the gate pattern 68, 108 and 134 a can be controlled byproviding a spacer on sidewalls of the gate pattern 68, 108 and 134 a.

FIGS. 4A through 9A are plan views illustrating processing steps in thefabrication of transistors according to some embodiments of the presentinvention. FIGS. 4B through 9B are cross sections taken along the lineA-A′ in FIGS. 4A through 9A. Referring to FIGS. 4A and 4B, a sacrificialpattern 52 having an opening 54 is formed on the integrated circuitsubstrate 50. An active region is defined by the opening 54. A firstepitaxial layer 56 and a second epitaxial layer 58 are sequentiallyformed on the integrated circuit substrate 50 exposed in the opening 54.The first epitaxial layer 56 and the second epitaxial layer 58 may havea lattice constant similar to the integrated circuit substrate 50. Thefirst epitaxial layer 56 and the second epitaxial layer 58 have etchingselectivities with respect to each other. In other words, the firstepitaxial layer 56 may be, for example, a silicon germanium epitaxiallayer, and the second epitaxial layer 58 may be, for example, a siliconepitaxial layer.

Referring now to FIGS. 5A and 5B, a mask layer 60 is formed on a surfaceof the integrated circuit substrate 50. The mask layer 60 is patternedto form a gate opening 62 on the active region and the sacrificial layer52. The second epitaxial layer 58 and the first epitaxial layer 56 areetched in the gate opening 62 to expose the integrated circuit substrate50. As illustrated in FIG. 5B, the integrated circuit substrate 50includes the first and second epitaxial layers 56 and 58 stacked on theactive region on both sides of the gate opening 62.

Referring now to FIGS. 6A and 6B, a third epitaxial layer 64 is formedon the exposed portion of the integrated circuit substrate 50. The thirdepitaxial layer 64 has an etching selectivity with respect to the firstepitaxial layer 56. The third epitaxial layer 64 may be, for example, asilicon epitaxial layer. The third epitaxial layer 64 may be grown fromthe first and second epitaxial layers 56 and 58 and the surface of theexposed portion of the integrated circuit substrate 50. Accordingly, thethird epitaxial layer 64 can be grown to have low recess region relativeto a bottom surface of the second epitaxial layer 58 by controlling thegrowing time.

Referring now to FIGS. 7A and 7B, a gate insulation layer 66 is formedafter partially channel doping to the third epitaxial layer 64. Aconductive layer is formed on the integrated circuit substrate 50including the gate insulation layer 66. A gate pattern 68 is formed inthe gate opening 62 by polishing the conductive layer. The conductivelayer may be polished by applying, for example, a chemical mechanicalpolishing process. The conductive layer may include a polysilicon layer,metal layer, metal silicide layer and/or polycide layer. The gatepattern 68 is provided on the gate insulation layer as well as thesacrificial pattern 52. As illustrated in FIGS. 8A and 8B, theconductive layer may be formed in the gate opening 62 after forminginner spacers 67 on sidewalls of the gate opening 62. In certainembodiments of the present invention, the conductive pattern 68 havinginner spacers 67 defines the gate pattern. In this structure, a gateinduced breakdown leakage (GIBL) current resulting from overlapping withthe gate pattern by diffusing impurities of the source and drain regionscan be reduced. Furthermore, the transistor can be formed withrelatively short channel length.

Referring now to FIGS. 9A and 9B, the mask layer 60 and the sacrificiallayer 52 are removed. As a result, a portion of the first epitaxiallayer 56 is exposed, and the surface of the gate pattern 68 and thesurface of the second epitaxial layer 58 is exposed. The first epitaxiallayer 56 is removed using, for example, an isotropic etching method. Abottom surface of the second epitaxial layer 58 is exposed by removingthe first epitaxial layer 56 because the first epitaxial layer 56 has anetching selectivity with respect to the second epitaxial layer 58. Thesecond epitaxial layer 58 extends on the integrated circuit substrate 50to form parallel fin shapes on the third epitaxial layer 64.

As further illustrated in FIGS. 9A and 9B, an oxide layer 70 is formedin the gap region between the second epitaxial layer 58 and theintegrated circuit substrate 50. The oxide layer 70 may be formed in thegap region using, for example, a thermal oxidation process on theintegrated circuit substrate.

Referring now to FIGS. 10A and 10B, the source and drain regions 74 areformed in the second epitaxial layer 58. The source and drain regions 74are formed by using the gate pattern 68 as an ion implantation mask andimplanting impurities into the integrated circuit substrate 50. Thesource and drain regions 74 are formed with, for example, a lightlydoped drain (LDD) structure or double-diffused drain (DDD) structure byforming the spacer 72 on a portion of the gate pattern 68. In addition,a silicide layer may be optionally formed on the surface of the sourceand drain regions 74.

In certain embodiments of the present invention, during the ionimplantation process, an impurity diffusion layer can be formed on theintegrated circuit substrate 50 adjacent to the second epitaxial layer68. The impurity diffusion layer may cover the active region and mayreduce the likelihood of punch through between neighboring transistors.

Referring again to FIGS. 10A and 10B, the insulation layer 76 is formedon a surface of the integrated circuit substrate 50. The insulationlayer 76 may not only be used as the isolation layer on the peripheralactive region of the integrated circuit substrate, but may also be usedas an interlayer dielectric layer by covering the integrated circuitsubstrate 50 including the source and drain regions 74 and the gatepattern 68.

FIGS. 11A and 12A are plan views illustrating processing steps in thefabrication of transistors according to further embodiments of thepresent invention. FIGS. 11B and 12B are cross sections taken along theline B-B′ in FIGS. 11A and 12A. Referring now to FIGS. 11A and 11B, thefirst epitaxial layer 68 is formed on the exposed portion of theintegrated circuit substrate 50 after forming the sacrificial pattern 52defining the active region on the integrated circuit substrate 50 asdiscussed above with respect to FIGS. 3 through 10B. In furtherembodiments of the present invention, if the first epitaxial layer isformed to a predetermined thickness, a slope facet can be formed in anedge of the first epitaxial layer. If the second epitaxial layer (58 inFIG. 4B) is formed on the first epitaxial layer 86, the first epitaxiallayer 86 covered by the second epitaxial layer can remain in asubsequent process removing the first epitaxial layer 86. In otherwords, the second epitaxial layer protects a portion of the firstepitaxial layer 86. In order to reduce the likelihood that the facetwill be removed, sidewall spacers 78 are formed on sidewalls of theopening 54. Sidewalls spacers 78 cover a part of the first epitaxiallayer 86, that is, the facet of the first epitaxial layer.

Referring to FIGS. 12A and 12B, the second epitaxial layer 88 is formedon the first epitaxial layer 86 by, for example, applying a selectiveepitaxial growing process to the integrated circuit substrate 50including the sidewalls spacers 78.

Subsequent processes can be performed as discussed above with respect toFIGS. 3 through 10B. Sidewalls spacers 78 may be formed of materialshaving an etching selectivity with respect to the sacrificial pattern 52or the mask layer (60 in FIG. 5B). Therefore, the sidewalls spacers 78can be removed during the same process used to remove the sacrificialpattern 52 or the mask layer (60 in FIG. 5B).

FIGS. 13A through 16A are plan views illustrating processing steps inthe fabrication of transistors according to further embodiments of thepresent invention. FIGS. 13B through 16B are cross sections taken alongthe line C-C′ in FIGS. 12A through 15B, respectively. As illustrated inFIGS. 13A and 13B, the first epitaxial layer 92, the second epitaxiallayer 94 and the mask layer 96 are sequentially formed. The first andsecond epitaxial layers 92 and 94 may include the same materials as alattice constant of the integrated circuit substrate 90. In other words,the first epitaxial layer 92 may be, for example, a silicon germaniumepitaxial layer and the second epitaxial layer 94 may be, for example, asilicon epitaxial layer. The mask layer 96 may include, for example,silicon nitride.

Referring now to FIGS. 14A and 14B, the first epitaxial layer 92, thesecond epitaxial layer 94 and the mask layer 96 are patterned to form atrench that defines the active region 98. The first epitaxial layer 92,the second epitaxial layer 94 and the mask layer 96 are stacked on theactive region 98. In certain embodiments of the present invention, apart of the integrated circuit substrate may be etched after patterningthe first epitaxial layer 92. The isolation layer 100 may be formed byproviding the insulation layer in the trench. The isolation layer 100may be provided on the first and second epitaxial layers 92 and 94 andthe mask layer 96.

Referring now to FIGS. 15A and 15B, the gate opening 102 is formed by,for example, patterning a part of the mask layer 96 and the first andsecond epitaxial layers 92 and 94. A portion of the integrated circuitsubstrate 90 is exposed by the gate opening 102. Although notillustrated in the Figures, the gate opening 102 can be formed to crossover a surface of the isolation layer 100 by partially patterning thesurface of the isolation layer 100. The third epitaxial layer 104 isformed on the exposed portion of the integrated circuit substrate 90. Asdiscussed above with respect to FIGS. 3 through 10B, the third epitaxiallayer 104 is formed having a low recess region in relation to a bottomsurface of the second epitaxial layer by, for example, controlling thegrowing time.

The gate insulation layer 106 is formed on the third epitaxial layer104. A gate pattern 108 is formed in the gate opening. Although notillustrated in the Figures, a gate line, which directly contacts thegate pattern 108 and crosses over a top surface of the isolation layer100, may also be formed. However, if the gate opening is formed to crossover a top surface of the isolation layer, the gate pattern 108 alsocrosses over the top surface of the isolation layer. The gate pattern108 may include a polysilicon layer, metal layer and/or polycide layer.

Referring now to FIGS. 16A and 16B, the mask layer 96 is removed. Aportion of the first epitaxial layer 92 is exposed by recessing a partof the isolation layer 100. The first epitaxial layer 92 is removed. Thefirst epitaxial layer 92 may be removed by, for example, an isotropicetching because a portion of the first epitaxial layer 92 is exposed. Asa result, a bottom of the second epitaxial layer 94 and a portion ofsidewalls of the third epitaxial layer 104 are exposed. An insulationlayer 112 is formed in the gap regions between the second epitaxiallayer 94 and the integrated circuit substrate 90. The source and drainregions are formed on the second epitaxial layer 94, and the interlayerdielectric layer is formed on a surface of the integrated circuitsubstrate 90.

FIGS. 17A through 21A are plan views illustrating processing steps inthe fabrication of transistors according to some embodiments of thepresent invention. FIGS. 17D through 21B are cross sections taken alongthe line D-D′ in FIG. 16A through FIG. 20A, respectively. As illustratedin FIGS. 17A and 17B, the first epitaxial layer 122, the secondepitaxial layer 124 and the mask layer 126 are formed on the integratedcircuit substrate 120. The first and second epitaxial layers 122 and 124may include similar materials as discussed above with respect to FIGS. 3through 10B.

Referring now to FIGS. 18A and 18B, the first epitaxial layer 122, thesecond epitaxial layer 124 and the mask layer 126 are patterned to formthe gate opening 128 that exposes a portion of the integrated circuitsubstrate 120. The third epitaxial layer 130 is formed on the integratedcircuit substrate 120 in the gate opening 128. The third epitaxial layer130 may be formed to have a low recess region in relation to a bottomsurface of the second epitaxial layer by, for example, controlling agrowing time. The gate insulation layer 132 is formed on the thirdepitaxial layer 130. The conductive layer 134 is provided in the gateopening on the integrated circuit substrate 120.

Referring now to FIGS. 19A and 19B, the trench 142, the conductive layer124, the first and second epitaxial layers 122 and 124, the mask layer126 and a portion of the integrated circuit substrate 120 are patternedto form a trench that defines the active region. The active region 140has sidewalls aligned to sidewalls of the third epitaxial layer in onedirection and includes a portion of the integrated circuit substrate 120on both sides of the epitaxial layer 130 in another direction. A bottomof the second epitaxial layer 124 and a portion of a sidewall of thethird epitaxial layer 130 are exposed by removing the first epitaxiallayer 122.

Referring now to FIGS. 20A and 20B, the insulation layer is on a surfaceof the integrated circuit substrate 120 in the gap region 144 betweenthe second epitaxial layer 124 and the integrated circuit substrate 120.The insulation layer may be formed using, for example, a thermaloxidation process and then a chemical vapor deposition process. The masklayer 126 is exposed by, for example, etching the insulation layer andthe conductive layer 134. As illustrated in FIGS. 20B, a gate pattern isformed in the gate opening, and the isolation layer 146 is provided onperipherals of the active region 140.

Referring now to FIGS. 21A and 21B, the gate line 150 is formed. Thegate line 150 may directly contact the gate pattern 134 a and cross overa top surface of the isolation layer 146. The gate line 150 may includea polysilicon layer, a metal layer, a metal silicide layer and/or apolysilicide layer. The second epitaxial layer 124 is exposed byremoving the mask layer 126. The source and drain regions 148 are formedby implanting impurities in the exposed portion of the second epitaxiallayer 124. The source and drain regions 148 can be formed having a DDDstructure or an LDD structure. The spacer can be formed on a sidewall ofthe gate pattern 134 a. In addition, a silicide layer may be provided onthe gate line 150 and the source and drain regions 148.

As briefly discussed above with respect to FIGS. 3 through 21B,transistors according to embodiments of the present invention may have alow recessed channel region in relation to a bottom surface of thesource and drain regions. Thus, a channel length of transistorsaccording to embodiments of the present invention may be longer relativeto a gate line width, while still having a relatively short gate linewidth. Thus, the likelihood that transistors according to embodiments ofthe present invention may experience a short channel effect and/orpunch-through between the source and drain regions may be reduced.Furthermore, transistors according to embodiments of the presentinvention may provide source and drain regions having bottom surfacesthat contact at least a portion of the insulation pattern and a channelregion between the source and drain regions may be connected to theintegrated circuit substrate. Accordingly, transistors according toembodiments of the present invention may provide a reduced likelihood ofthe occurrence of the short channel effect and a floating body effectand may disperse heat throughout the device during operation of thetransistor. Furthermore, transistors according to embodiments of thepresent invention may have a gate pattern having sidewalls aligned withparallel fins that include the source and drain regions. This structuremay reduce the possibility of misalignment of the gate pattern and mayreduce characteristic dispersion of transistor in a cell array region.

In the drawings and specification, there have been disclosed typicalpreferred embodiments of the invention and, although specific terms areemployed, they are used in a generic and descriptive sense only and notfor purposes of limitation, the scope of the invention being set forthin the following claims.

1. A semiconductor device, comprising: a source/drain epitaxial layer ona semiconductor substrate; a channel epitaxial layer on thesemiconductor substrate, the channel epitaxial layer having a recessregion that is lower than a bottom surface of the source/drain epitaxiallayer; a gate on the channel epitaxial layer; and an insulating layerbetween the source/drain epitaxial layer and the semiconductor substrateand self-aligned to the gate.
 2. The device of claim 1, wherein a bottomsurface of the gate adjacent to the semiconductor substrate is lowerthan a top surface of the source/drain region.
 3. The device of claim 1,further comprising a spacer in a sidewall of the gate.
 4. The device ofclaim 1, further comprising an isolation layer, a bottom surface of theisolation layer being lower than a bottom surface of the source/drainepitaxial layer.